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-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:17:55 04/20/2012 
-- Design Name: 
-- Module Name:    flags - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity flags is
    Port ( int_ZF : in  STD_LOGIC; -- Las que vienen del reg de interrupciones (cuando is_end_interrupt esta activo)
           int_CF : in  STD_LOGIC;
           alu_ZF : in  STD_LOGIC; -- Las que vienen de la ALU como resultado de la operacion.
           alu_CF : in  STD_LOGIC;
           enable : in  STD_LOGIC; -- Solo nos activa la unidad de control en EXECUTE
           clk : in  STD_LOGIC;
			  reset: in STD_LOGIC;
			  is_end_interrupt: in  STD_LOGIC; -- Activo cuando se ha terminado la interrupcion, la carga de los flags
															-- que estaban en el reg de interrupciones.		
				CF: out STD_LOGIC; -- Esta senyal debe ir a 2 sitios (registro de instrucciones y ALU)
				ZF: out STD_LOGIC
			  
			  );
end flags;

architecture Behavioral of flags is

begin

process (clk,reset) begin

	if reset ='1' then 
		ZF <= '0';
		CF <= '0';
	elsif clk'event  and clk = '1' then 
		if enable = '1' then 
			if is_end_interrupt = '1' then
				CF <= int_CF;
				ZF <= int_ZF;	
			else
				CF <= alu_CF;
				ZF <= alu_ZF;	
			end if;
		end if;
	end if;
end process;

end Behavioral;

